The MC14526B binary counter is constructed with MOS P−channel and N−channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded “0” state output for divide−by−N applications. Insingle stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide−by−N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.

Features of CD4526 Divide-By-N Counter:

• Internally Synchronous for High Speed.
• Logic Edge-Clocked Design Increments on Positive Clock Transistion.
• Clock Inhibit Pin.
• Wide Operating Voltage Range.
• Low Power TTL.

Applications of CD4526 Divide-By-N Counter:

• Frequency synthesizers.
• Phase-locked loops.
• Programmable down counters.
• Programmable frequency dividers.